Voltage multiplier

ABSTRACT

The present invention relates to a voltage multiplier for generating an output voltage which is several times greater than the operating voltage for connection of a load connected to ground to the operating voltage by means of an N-channel power MOS transistor, comprising a plurality of capacitors (C1, C2, C3), a control input (C) for supplying a control signal, an output (V out ), an operating voltage terminal (Vb) and a ground terminal (M). In known voltage multipliers, for rectification and multiplication of the output voltage diodes are used which reduce the maximum output voltage obtainable and restrict the clock frequency of the control signal to a few hundred kHz. In contrast, the voltage multiplier according to the invention has a high efficiency and can also be used at high clock frequencies; it includes a switchover means which comprises a control signal generator (S) having a plurality of inverters (I0, I1, I2, I3) and a first and second group of switch elements which are constructed as MOS field-effect transistors and can be driven with clock frequencies of up to 4 MHz. These MOS field-effect transistors are controlled by means of the control signal generator (S) by control signals in such a manner that the capacitors are periodically switched between a series connection and a parallel connection.

This application is a continuation of application Ser. No. 08/041,026,filed Mar. 31, 1993, now abandoned.

The invention relates to an integrated voltage multiplier for generatingan output voltage which is several times greater than the operatingvoltage for connecting a load connected to ground to the operatingvoltage by means of an N-channel power MOS transistor, comprising aplurality of capacitors, a control input for supplying a clock signal,an output, an operating voltage terminal and a ground terminal.

Voltage multipliers are widely used in almost all areas of electricalengineering. For example, in motor vehicle systems it is frequentlynecessary to connect loads which are connected to ground to theoperating voltage via an electronic switch without a voltage droparising at the closed switch in order to ensure that the voltage drop atthe load is as far as possible equal to the operating voltage.

In general, N-channel power MOS field-effect transistors are used aselectronic switches for connecting the loads to the operating voltage,because P-channel MOS field-effect transistors with a low drain-sourceresistance are not available on monolithic integrated semiconductorcircuits and consequently the voltage drop at the drain-source path ofthe N-channel MOS field-effect transistor is too high.

The necessary low voltage drop is achieved in the N-channel transistorsin that the gate electrode of the power MOS field-effect transistor usedas a power switch is connected to a voltage potential which is higherthan the operating voltage potential. This means however, in practicethat voltages of more than 15 V must be present on monolithic integratedsemiconductor circuits on which only an operating voltage of about 5 Vis available.

To generate on monolithic integrated semiconductor circuits voltageswhich are higher than the operating voltage, voltage multipliers areemployed which are generally integrated into the semiconductor circuitand include a plurality of lateral bipolar diodes. The circuitconfiguration of such a voltage multiplier is for example shown in FIG.1.

The circuit illustrated in FIG. 1 represents a voltage multiplier whichcomprises a control input C, an output and an operating voltage terminalB and which includes of four diodes D1 to D4, three capacitors C1 to C3and three inverters I1-I3. The output of the voltage multiplier isconnected to the gate electrode of an MOS field-effect transistor whichserves as a switch for switching the load R_(L) to the operating voltageVb. The three inverters are connected in series and controlled via thecontrol input C.

If the voltage multiplier illustrated in FIG. 1 is connected to theoperating voltage and the control input C of the voltage multiplier isin the L state, firstly the capacitor C2 and the gate capacitance of theMOS field-effect transistor acting as a capacitor are charged. If thecontrol input changes to the H state, the outputs of the inverters I1and I3 change to the L state and the capacitors C1 and C3 areconsequently charged. The charge quantities Q1, Q2 and Q3 stored in therespective capacitors C1, C2 and C3 are conveyed when the capacitors aredischarged via the diodes D2-D4 to the gate electrode of the MOSfield-effect transistor so that a charge quantity Q1+Q2+Q3 isadditionally added to the charge quantity Q4 already present in the gateelectrode. If this transfer charging process is carried out with highenough clock frequency, on a time average at the gate electrode a chargequantity Q corresponding to the sum of the individual charges Q1 to Q4is present which generates at the gate electrode of the field-effecttransistor a voltage corresponding to a multiple of the operatingvoltage.

The known voltage multiplier according to FIG. 1 has however the seriousdisadvantage that lateral bipolar diodes D1 to D4 are necessary forrectifying the voltages at the capacitors C1 to C3. Lateral diodes areused because they have reverse voltages of the order of magnitude of theoperating voltage. However, lateral diodes have relatively longswitch-through times so that the clock frequency supplied to the controlinput C for reverse charging of the capacitors C1 to C3 is limited to a20 few hundred kHz. Furthermore, when using this voltage multiplier inan integrated semiconductor circuit the lateral diodes give rise toparasitic effects which are initiated by vertical substrate PNPtransistors which are connected when the lateral diodes are operated inthe forward direction. A further disadvantage is to be seen in that theuse of silicon diodes reduces the voltage multiplied at the output byeach diode by 0.7 V so that the efficiency of the known voltagemultiplier is not more than 60 to 80%.

In view of these disadvantages the problem underlying the invention isto provide an integrated voltage multiplier which can be used at highfrequencies and has high efficiency.

In a voltage multiplier for generating an output voltage which isseveral times greater than the operating voltage for connecting a loadconnected to ground to the operating voltage by means of an N-channelpower MOS transistor, comprising a plurality of capacitors, a controlinput for supplying a clock signal, an output, an operating voltageterminal and a ground terminal this problem is solved, by the featuresthat the output is connected via a unidirectionally conductive circuitelement to the operating voltage terminal, that a switchover means isprovided which comprises a control signal generator and a first group ofswitch elements having control terminals which are connected to one ormore outputs of the control signal generator so that the first group ofswitch elements are switchable by means of control signals from thecontrol signal generator between a conductive and a nonconductive state,and a second group of switch elements having control terminals which areconnected to a further output of the control signal generator so thatthe second group of switch elements are switchable by means of a furthercontrol signal from the control signal generator between a conductiveand a nonconductive state, that in each case two of the switch elementsof the first group of switch elements connect the positive and thenegative electrode of a capacitor to the operating voltage terminal andthe ground terminal respectively, that the switch elements of the secondgroup are connected to the capacitors in such a manner that they form aseries circuit between the operating voltage terminal and the output inwhich a respective switch element and a capacitor lie alternately, andthat the two groups of switch elements are driven by the control signalgenerator in such a manner that they are alternately in the conductiveand in the nonconductive state and during the operation have oppositestates.

Advantageous further developments of the invention are characterized indetail in the subsidiary claims.

Hereinafter an example of embodiment of the invention will be explainedin detail with the aid of the drawings, wherein:

FIG. 1 shows a conventional voltage multiplier,

FIG. 2 shows an embodiment of the voltage multiplier according to theinvention,

FIG. 3 shows the embodiment of FIG. 2 in a first state and

FIG. 4 shows the embodiment of FIG. 2 in a second state.

In contrast to the known voltage multiplier shown in FIG. 1, in whichthe rectification and addition of the capacitor currents is by means oflateral diodes, in the voltage multiplier illustrated in FIG. 2 aswitchover means comprising MOS field-effect transistors is provided bywhich the capacitors C1-C3 are connected together in series so that thecapacitor voltages are summated.

As apparent from FIG. 2, the voltage multiplier comprises the capacitorsC1, C2 and C3 for generating an output voltage V_(out) which is severaltimes greater than the operating voltage Vb, an operating voltageterminal B, a ground terminal M, a control input C for supplying a clocksignal and an output A to which the gate electrode of an N-channel powertransistor N1 is connected.

The voltage multiplier of FIG. 2 further includes for switching over thecapacitors C1, C2 and C3 a switchover means which comprises a circuitsection S and a plurality of switch elements having control terminalswhich are controlled by control signals by means of the control signalgenerator S in such a manner that the capacitors C1, C2 and C3 areperiodically switched between a parallel circuit and a series circuit.The control signal generator S includes a plurality of inverters I0, I1,I2 and I3, an input connected to the control input C of the voltagemultiplier and a first, second and third output for furnishing controlsignals, the control input C being the inverter input of an inputinverter I0 and the first, second and third outputs being the outputs ofa first, second and third inverter I1, I2 and 13.

The switch elements are preferably formed by MOS field-effecttransistors N12 to N19 and P13 to P21. Via the N-channel power MOSfield-effect transistor N1 serving as electronic switch a load R_(L) canbe connected to the output A of the voltage multiplier. If the voltagemultiplier 20 in operation, the output voltage V_(out) increasedcompared with the operating voltage Vb is present at the output thereofand consequently the transistor N1 opens and connects the load R_(L) tothe operating voltage Vb.

Each capacitor C1, C2 and C3 of the voltage multiplier is connected totwo MOS field-effect transistors N12 and P14, N16 and P17, N19 and P20,used as switch elements, of a first group of switch elements and to thesource-drain paths thereof in series, so that the negative electrodes ofthe capacitors C1, C2 and C3 are each connected via a drain-source pathof the N-channel field-effect transistors N12, N16 and N19--which form afirst subgroup of the first group of switch elements-to the massterminal M when the field-effect transistors N12, N16, N19 of saidsubgroup are in the conductive state. The positive electrodes of thecapacitors C1, C2 and C3 are each connected via the drain-source pathsof the P-channel field-effect transistors P14, P17 and P20--which formanother subgroup of a first group of switch elements--to the operatingvoltage terminal B when the field-effect transistors of the othersubgroup are in the conductive state, i.e. when the P-channeltransistors P14, P17 and P20 are in the conductive state.

A second group of switch elements of the voltage multiplier is formed byP-channel MOS field-effect transistors P13, P15, P18 and P21. Thedrain-source paths of these transistors and the capacitors C1, C2 and C3are connected alternately in series so that they form a series circuitbetween the operating voltage terminal B and the output A, in which arespective switch element and a capacitor alternately lie. The MOSfield-effect transistors P13 and P21 connect the capacitor C1 and thecapacitor C3 to the operating voltage terminal B and to the output Arespectively when the transistors P13 and P21 are in the conductivestate.

Hereinafter the mode of operation of the voltage multiplier illustratedin FIG. 2 will now be described in detail.

To make an output voltage higher than the operating voltage available atthe output of the voltage multiplier, as already mentioned the switchingstate of the field-effect transistors of the first group and of thesecond group are periodically changed in such a manner that thecapacitors are switched alternately from a parallel connection to aseries connection. If the clock signal present at the control input C isin the H state, the field-effect transistors of the first group areconductive and the field-effect transistors of the second group arenonconductive so that the capacitors C1, C2 and C3 are connected inparallel to each other and lie in each case between the operatingvoltage terminal B and the ground terminal M. Each capacitor is chargedthereby to the operating voltage Vb. If the clock signal present at thecontrol input is in the L state, the field-effect transistors of the twogroups assume opposite switching states so that the capacitors C1, C2and C3 are connected in series and the capacitor C1 is connected via thetransistor P13 to the operating voltage terminal B and the capacitor C3via the transistor P21 to the output A. There is then a voltage drop ofapproximately 4 Vb between the output A and ground M.

The first state of the voltage multiplier (control signal input C: H)will be explained in detail hereinafter with the aid of FIG. 3. When thevoltage multiplier is connected to the operating voltage Vb, a chargingcurrent flows via the transistor P22 to the gate capacitor (capacitanceof the gate electrode of N1) of the transistor N1 serving as switch,which is connected between output and ground terminal. After completionof this charging operation the output voltage at the output A has risento a voltage value V_(out) which can be calculated in accordance withthe following equation:

    V.sub.out =Vb-V.sub.P22                                    (1)

In this equation, V_(P22) is the voltage drop at the drain-source pathof the transistor P22.

Now, when the clock signal at the control input C of the voltagemultiplier is in the H state, the outputs of the inverters I3 and I1 arein the L and H state respectively. Consequently, the gate-sourcevoltages of the P-channel transistors of the one subgroup are negativeand those of the N-channel transistors of the other subgroup arepositive so that the transistors P14, P17 and P20 and the transistorsN12, N16 and N19 are rendered conductive and connect the positiveelectrodes and the negative electrodes of the capacitors C1, C2 and C3to the operating voltage terminal A and to the ground terminal Mrespectively.

The capacitors C1, C2 and C3 then connected in parallel are nowsimultaneously charged up to the operating voltage Vb. The period of theclock signal here must be dimensioned so that the charging time requiredto charge the capacitors is shorter than the half period of the clocksignal. The transistors of the second group of switch elements, i.e. theP-channel transistors P13, P15, P18 and P21, are all nonconductive hereso that the electrical connections between the capacitors C1, C2 and C3are interrupted. This is achieved in that the further output of theinverter 12 connected to the gate electrodes of said transistors is inthe H state during the first switching state and this ensures that thegate-source voltages of the P-channel transistors are positive so thatthe transistors P13, P15, P18 and P21 remain in the nonconductive state.

Hereinafter, with reference to FIG. 4 the second state of the voltagemultiplier (control signal input C:L) will be described. When the clocksignal at the control input C changes its electrical state and goes intothe L state, the outputs of the inverters I1 and I3 are switched to theL state and the H state respectively. The result of this is that thegate voltages of the N-channel transistors N12, N16 and N19 drop toground potential so that said transistors are changed to thenonconductive state and interrupt the electrical connections between thenegative electrodes of the capacitors and the ground terminal. TheP-channel transistors P14, P17 and P20 are likewise nonconductive andinterrupt the electrical connections between the positive electrodes ofthe capacitors and the operating voltage terminal B, since thegate-source voltages of said capacitors are positive when the output ofthe inverter 13 is in the H state.

However, the P-channel transistors P13, P15, P18 and P21 are in theconductive state here because the output of the inverter I2 connected tothe gate electrodes of said transistors is in the L state during thesecond switching state and consequently the gate-source voltages of theP-channel transistors P13, P15, P18 and P21 are negative. The negativeelectrode of the capacitor C1 is thus connected to the operating voltageterminal B and the capacitors C1, C2 and C3 are connected in series; thepositive electrode of the capacitor C3 is connected to the output A ofthe voltage multiplier. Accordingly, the capacitors fully charged duringthe first switching state and now connected in series charge the gatecapacitor of the transistors N1 to such an extent that the gate voltageof the transistor N1 rises to four times the operating voltage. For thecharging voltage at the series-connected 20 capacitors C1, C2 and C3,which are each charged to the operating voltage Vb, is added to saidoperating voltage. Consequently, at the output A of the voltagemultiplier a voltage V_(out) can be tapped off which correspondsapproximately to four times the operating voltage Vb.

If V_(out) <Vb, during the charging of the capacitors C1, C2 and C3 acurrent also flows via the transistor P22 to the output A of the voltagemultiplier and consequently the output voltage V_(out) rises during thecharging of the capacitors and thus prevents discharging of saidcapacitors. Consequently, the capacitor voltages after the charging areeach equal to Vb so that directly after the switchover to the seriesconnection the charge voltage between the negative electrode of thecapacitor C1 and the positive electrode of the capacitor C3 is 3 Vb.

An optimum functioning of the voltage multiplier requires that the MOSfield-effect transistors and in particular the P-channel MOSfield-effect transistors open and close completely. Consequently, thecontrolling gate electrodes of the P-channel transistors must beconnected to the highest voltage available in the voltage multiplier. Inthe present example of embodiment the highest available voltage is atthe output A which via the 9ate electrode of the transistor P22connected as diode is always electrically connected to the conductor L1.For the same reason, the gate electrodes of all the P-channeltransistors require control voltages which lie above the operatingvoltage Vb. For this reason the operating voltage terminals of theinverters I1, I2 and I3 are connected to the conductor L1. This is theonly way of ensuring that the control voltages at the gate electrodes ofthe MOS field-effect transistors are higher than the operating voltageVb in the respective necessary cases.

The voltage multiplier of the type described can be operated with highclock frequencies. The clock frequencies may be up to 4 MHz, since theMOS field-effect transistors used can be switched very rapidly from theconductive to the nonconductive state.

I claim:
 1. An integrated voltage multiplier for generating an outputvoltage greater in magnitude by a multiple of the operating voltage forconnecting a load connected to ground to the operating voltage via anN-channel power MOS transistor, said voltage multiplier comprising:acontrol input for providing a clock signal; an output; an operatingvoltage terminal; a ground terminal; a unidirectionally conductivecircuit element interposed between the operating voltage terminal andthe output and respectively connected thereto; switch over meanscomprising a control signal generator; a first group of switch elementshaving control terminals connected to respective outputs of said controlsignal generator; said first group of switch elements being switchablein response to the generation of respective control signals from saidcontrol signal generator and applied to the control terminals of saidfirst group of switch elements so as to switch said first group ofswitch elements between a conductive and a nonconductive state; a secondgroup of switch elements having control terminals connected to a furtheroutput of said control signal generator; said second group of switchelements being switchable between a conductive and a nonconductive statein response to the application of a further control signal from saidcontrol signal generator to the control terminals of said second groupof switch elements; a plurality of capacitors operably interconnectedbetween said first and second groups of switch elements; respectivepairs of switch elements included in said first group of switch elementsconnecting the positive and the negative electrodes of a capacitorcorresponding thereto to said operating voltage terminal and to saidground terminal respectively; said switch elements of said second groupof switch elements being connected to said plurality of capacitors toform a series circuit of said plurality of capacitors between saidoperating voltage terminal and the output having a respective switchelement of said second group of switch elements and a capacitor of saidplurality of capacitors arranged in an alternating sequence; said firstand second groups of switch elements being driven by the respectivecontrol signals from said control signal generator in an alternatingsequence such that said first and second groups of switch elements arealternately in the conductive and in the nonconductive states whereinsaid first group of switch elements are in the conductive state whensaid second group of switch elements are in the nonconductive state andvice-versa.
 2. A voltage multiplier as set forth in claim 1, whereinsaid control signal generator comprises a plurality of inverters andhaving an input connected to the control input and first, second andthird outputs for providing control signals;said plurality of invertersproviding inverter outputs as the first, second and third outputs ofsaid control,signal generator, respectively.
 3. A voltage multiplier asset forth in claim 1, wherein the first output of said control signalgenerator is connected to the control terminals of switch elementsincluded in a subgroup of the first group of switch elements;the secondoutput of said control signal generator providing the further controlsignal of said control signal generator connected to the controlterminals of said second group of switch elements; the third output ofsaid control signal generator being connected to the control terminalsof another subgroup of said first group of switch elements.
 4. A voltagemultiplier as set forth in claim 3, wherein the switch elements of saidone subgroup of said first group of switch elements are N-channel, MOSfield-effect transistors;the switch elements of the other subgroup ofsaid first group of switch elements are P-channel MOS field-effecttransistors; the switch elements of said second group of switch elementsare P-channel MOS field-effect transistors.
 5. A voltage multiplier asset forth in claim 4, wherein said unidirectionally conductive circuitelement is a P-channel MOS field-effect transistor.
 6. A voltagemultiplier as set forth in claim 5, wherein said plurality of inverterscomprising said control signal generator are respectively provided withoperating voltage terminals;the operating voltage terminals of saidplurality of inverters being connected to said output, to the gateelectrode of said P-channel MOS field-effect transistor and to groundterminal.